科研之友
微信
新浪微博
Facebook
分享链接
摘要
Finite field multiplication is one of the most important operations in the finite field arithmetic and the main and determining building block in terms of overall speed and area in public key cryptosystems. In this work, an efficient and high-speed VLSI implementation of the bit-serial, digit-serial and bit-parallel optimal normal basis multipliers with parallel-input serial-output (PISO) and parallel-input parallel output (PIPO) structures are presented. Two general multipliers, namely, Massey-Omura (MO) and Reyhani Masoleh-Hassan (RMH) are considered as case study for implementation. These multipliers are constructed by using AND, XOR-AND and XOR tree components. In the MO multiplier, to have strong input signals and have a better implementation, the row of AND gates are implemented by using inverter and NOR components. Also the XOR-AND component in the RMH structure is implemented using a new low-cost structure. The XOR tree in both multipliers consists of a high number of logic stages and many inputs; therefore, to optimally decrease the delay and increase the drive ability of the circuit for different loads, the logical effort method is employed as an efficient method for sizing the transistors. The multipliers are first designed for different load capacitances using different structures and different number of stages. Then using the logical effort method and a new proposed 4-input XOR gate structure, the circuits are modified for acquiring minimum delay. Using 0.18 pm CMOS technology, the bit-serial, digit serial and bit-parallel structures with type-1 and type-2 optimal normal basis are implemented over the finite fields GF(2(226)) and GF(2(233)) respectively. The results show that the proposed structures have better delay and area characteristics compared to previous designs.
- 出版日期2016-9
