A time digitizer for space instrumentation using a field programmable gate array

作者:Rogacki S*; Zurbuchen T H
来源:Review of Scientific Instruments, 2013, 84(8): 083107.
DOI:10.1063/1.4818965

摘要

Space instruments such as time-of-flight (TOF) mass spectrometers and altimeters rely on time-to-digital converters (TDCs) to measure accurately times in the picosecond to microsecond range. Time-to-digital conversion is often implemented with analog circuitry or more recently with custom ASIC (Application Specific Integrated Circuit) devices. The analog approach may be costly in terms of circuit board area and parts count, while ASIC development is risky and costly when system requirements may change. Here, we present a highly flexible, accurate, and low-cost field-programmable gate array (FPGA) implementation of such TDC functionality. Compared with other technologies, this method reduces the parts count in TOF-supporting circuits and provides design flexibility in TOF instrumentation, especially for use in space or for applications with a number of sensors too small to warrant the development of a dedicated ASIC. Our technique can accommodate one or more STOP pulse measurements for each START pulse as signal reference, effectively providing measurements of multiple times-of-flight with the same start trigger. Alternatively, all pulse event edges can receive an absolute time stamp, enabling a broad set of new sensor applications. This novel design is based on the construction of a delay-line internal to the FPGA. Propagation variations due to temperature and supply voltage, which typically limit FPGA-based timing designs, are automatically compensated, allowing active signal processing 100% of the time. A methodology for the characterization of internal delay-line timing and nonlinearity has also been developed and is not specific to a particular FPGA architecture. We describe the design of this FPGA-based TDC and also describe detailed tests with a Xilinx XC2V1000. For single non-repetitive events, this design achieves 60 ps accuracy (standard deviation of error); a simplified implementation is suitable for non-reprogrammable FPGAs.

  • 出版日期2013-8