A Low Nonlinearity, Missing-Code Free Time-to-Digital Converter Based on 28-nm FPGAs With Embedded Bin-Width Calibrations

作者：Chen, Haochang^*; Zhang, Yongliang; Li, David Day-Uei

来源：IEEE Transactions on Instrumentation and Measurement, 2017, 66(7): 1912-1921.

DOI：10.1109/TIM.2017.2663498

• Carry chains
• code bin width
• field-programmable gate arrays (FPGA) multiphase clock
• time-of-flight
• time-to-digital converters (TDCs)

This paper presents a low nonlinearity, missingcode free, time-to-digital converter (TDC) implemented in a 28-nm field programmable gate array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the nonuniformity originated from carry chains, and use a multiphase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [-0.38, 0.87] LSB (the least significant bit: 10.5 ps) with sigma DNL = 0.20 LSB, and the integral nonlinearity (INL) is within [-1.23, 1.02] LSB with sigma INL = 0.50 LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNLpk-pk (peak-to-peak DNL) and INLpk-pk (peak-to-peak INL) can be reduced to 0.08 LSB with sigma DNL = 0.01 and 0.13 LSB with sigma INL = 0.02 LSB, respectively.

• 出版日期2017-7
• 单位浙江大学