An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure

作者：Byun Yong Ki^*; Park Jong Kang; Kwon Soongyu; Kim Jong Tae

来源：Journal of Semiconductor Technology and Science, 2013, 13(1): 8-14.

DOI：10.5573/JSTS.2013.13.1.008

• Low-density parity-check(LDPC) codes
• FEC
• upper dual-diagonal
• quasi-cyclic

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon%26apos;s limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• 出版日期2013-2