A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 mu s Frequency Acquisition Time

作者：Jung Inhwa^*; Shin Daejung; Kim Taejin; Kim Chulwoo

来源：IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(7): 1310-1315.

DOI：10.1109/TVLSI.2010.2047953

• Clock and data recovery (CDR)
• embedded clock
• linear PD
• low-jitter
• low voltage differential signaling (LVDS)
• transceiver
• wide-range

This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 mu s. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm(2) in a 0.25-mu m 1P5M CMOS technology.

• 出版日期2011-7