A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy

作者：Chen Yuan Ho^*; Chang Tsin Yuan

来源：IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(4): 655-664.

DOI：10.1109/TVLSI.2011.2110620

• Binary signed-digit (BSD)
• discrete cosine transform (DCT)
• distributed arithmetic (DA)-based
• space-time scheduling (STS)

In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS) strategy, that achieves high image resolutions in real-time systems is proposed. The proposed spatial scheduling strategy includes the ability to choose the distributed arithmetic (DA)-precision bit length, a hardware sharing architecture that reduces the hardware cost, and the proposed time scheduling strategy arranges different dimensional computations in that it can calculate first-dimensional and second-dimensional transformations simultaneously in single 1-D discrete cosine transform (DCT) core to reach a hardware utilization of 100%. The DA-precision bit length is chosen as 9 bits instead of the traditional 12 bits based on test image simulations. In addition, the proposed hardware sharing architecture employs a binary signed-digit DA architecture that enables the arithmetic resources to be shared during the four time slots. For this reason, the proposed 2-D DCT core achieves high accuracy with a small area and a high throughput rate and is verified using a TSMC 0.18-m 1P6M CMOS process chip implementation. Measurement results show that the core has a latency of 84 clock cycles with a 52 dB peak-signal-to-noise-ratio and is operated at 167 MHz with 15.8 K gate counts.

• 出版日期2012-4
• 单位清华大学