A parallel-layered belief-propagation decoder for non-layered LDPC codes

作者：Guo Kun^*; Hei Yong; Qiao Shushan

来源：Journal of Communications, 2010, 5(5): 400-408.

DOI：10.4304/jcm.5.5.400-408

• Average power
• Clock frequency
• CMOS technology
• Core size
• Decoder architecture
• Die area
• Error performance
• Flooding algorithms
• Layered decoding
• LDPC codes
• LDPC decoder
• Low Power
• Low-density parity-check codes
• Multi rate
• Parallel decoder
• Quasi-cyclic
• Quasicyclic codes

In this paper, we proposed a Parallel-Layered Belief-Propagation (PLBP) algorithm first, which makes a breakthrough in utilizing the layered decoding algorithm on the "non-layered" quasi-cyclic (QC) LDPC codes, whose column weights are higher than one within layers. Our proposed PLBP algorithm not only achieves a better error performance, but also requires almost 50% less iterations, compared with the original flooding algorithm. Then we propose a low-power partial parallel decoder architecture based on the PLBP algorithm. The PLBP decoder architecture requires less area and energy efficiency than other existing decoders. As a case study, a multi-rate 9216-bit LDPC decoder is implemented in SMIC 0.13μm 1P6M CMOS technology. The decoder dissipates an average power of 87mW with 10 iterations at a clock frequency of 83.3 MHz. The chip core size is 7.59 mm2, and the die area occupies 10.82 mm2.

• 出版日期2010