A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits

作者：Bai Xu^*; Kameyama Michitaka

来源：IEICE - Transactions on Electronics, 2013, E96C(8): 1083-1093.

DOI：10.1587/transele.E96.C.1083

• fine-grain reconfigurable VLSI architecture
• multiple-valued switch block
• binary-controlled current-steering technique
• current-source sharing technique
• current-mode logic (CML)

This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

• 出版日期2013-8