A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 mu m CMOS Technology

作者：Yu Jianjun^*; Dai Fa Foster; Jaeger Richard C

来源：IEEE Journal of Solid-State Circuits, 2010, 45(4): 830-842.

DOI：10.1109/JSSC.2010.2040306

• Digital phase locked loop (DPLL)
• frequency synthesis
• time and phase measurement
• time-to-digital converter (TDC)
• Vernier

A 12-bit Vernier ring time-to-digital converter (TDC) with time resolution of 8 ps for digital-phase-locked-loops (DPLL) is presented. This novel Vernier ring TDC places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. The proposed TDC thus achieves large detectable range, fine time resolution, small die size and low power consumption simultaneously. A pre-logic unit is developed to measure both positive and negative phase errors for DPLL applications. The TDC achieves a large detectable range of 12 bits with core area of 0.75 x 0.35 mm(2) in a 0.13 mu m CMOS technology. The total power consumption for the entire TDC chip is only 7.5 mW with a 1.5 V power supply, while operating at a clock frequency of 15 MSPS.

• 出版日期2010-4