A 12 b 8 kS/s 16 mu W 0.35 mu m CMOS algorithmic ADC for sensor interface in ubiquitous environments

作者：Kim Young Ju; Lee Seung Hoon^*

来源：Analog Integrated Circuits and Signal Processing, 2010, 62(2): 205-213.

DOI：10.1007/s10470-009-9343-5

• ADC
• CMOS
• Algorithmic
• Switched bias
• Low power
• Sensor

This work proposes a 12 b 8 kS/s ultra-low-power CMOS algorithmic analog-to-digital converter ( ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, low-power, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature-and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 mu m 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm(2) consumes 16 mu W at 8 kS/s and 2.5 V.

• 出版日期2010-2