A 0.039 mm(2) Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-Sigma Delta-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

作者：Zeller Sebastian^*; Muenker Christian; Weigel Robert; Ussmueller Thomas

来源：IEEE Journal of Solid-State Circuits, 2014, 49(7): 1548-1560.

DOI：10.1109/JSSC.2014.2321063

• Continuous-time (CT)
• digitally assisted
• integrator loss compensation
• IIR quantizer
• inverter-based
• JNR-DAC
• pseudo-differential
• quasi-1.5-bit
• Sigma Delta
• single-opamp

We present design techniques for the realization of compact, low-power CT-Sigma Delta-ADCs in ultra-deep-submicron CMOS: A resonant single-opamp third-order integrator with loss compensation, an inverter-based opamp with digitally assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization, a jitter-noise-reduction DAC with NRZ pulse shape, a mismatch-tolerant IIR quantizer, linearized single-ended FIR-DACs with passive DT compensation, and a rail-to-rail dynamic latched comparator. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic third-order modulator consists of only ten CMOS inverters.

• 出版日期2014-7