Design Space Exploration of 1-D FFT Processor

作者：Liu, Shaohan; Liu, Dake^*

来源：Journal of Signal Processing Systems for Signal Image and Video Technology, 2018, 90(11): 1609-1621.

DOI：10.1007/s11265-018-1393-4

• FFT (Fast Fourier Transform)
• Design space exploration
• Twiddle factor
• BFP (Block Floating Point)
• Non-power-of-two-point FFT

A design space exploration methodology of 1-D FFT processor is proposed to find the best hardware architecture in a quantitative way during early design. The methodology includes architecture candidate collection, coarse-grained architecture selection, and circuit level design optimizations. We show how to select a better architecture from candidates including different architectures (SDF, SDC, MDF, MDC and memory-based) with different degree of parallelism at different radices. The sub-level designs, including designs of rotator and data scaling module, are introduced for further optimizations. As a proof of concept, an FFT processor for 4G, WLAN and future 5G is designed supporting 16-4096 and 12-2400 point FFTs. Memory-based architecture with 16-datapath mixed-radix butterfly unit is selected to satisfy the demands for 1GS/s (4096) throughput. The synthesis result based on 65 nm technology shows that the silicon cost and power consumption are 1.46 mm 2 and 68.64 mW respectively. The proposed processor has better normalized throughput per area unit and normalized FFTs per energy unit than the state of the art available designs.

• 出版日期2018-11
• 单位北京理工大学