Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching

作者：Kim Woo Joo^*; Lee Sung Hee; Hwang Sun Young

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2009, E92A(3): 890-899.

DOI：10.1587/transfun.E92.A.890

• Network on Chip
• central routing
• circuit switching
• low-power switch
• hierarchical topology

This paper presents a hierarchical NoC architecture to support GT (Guaranteed Throughput) signals to process multimedia date in embedded systems. The architecture provides a communication environment that meets the diverse conditions of communication constraints among IPs in power and area. With a system based on packet switching, which requires storage/control circuits to support GT signals, it is hard to satisfy design constraints in area, scalability and power consumption. This paper proposes a hierarchical 4 x 4 x 4 mesh-type NoC architecture based on circuit switching, which is capable of processing GT signals requiring high throughput. The proposed NoC architecture shows reduction in area by 50.2% and in power consumption by 57.45% compared with the conventional NoC architecture based on circuit switching. These figures amount to by 72.4% and by 86.1%. when compared with an NoC architecture based off packet switching. The proposed NoC architecture operates in the maximum throughput of 19.2 Gb/s.

• 出版日期2009-3