A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With +/- 1.5% Frequency and +/- 3.6% Current-Sharing Error

作者：Sun Ming; Yang Zhe; Joshi Kishan; Mandal Debashis; Adell Philipe; Bakkaloglu Bertan

来源：IEEE Journal of Solid-State Circuits, 2017, 52(11): 3081-3094.

DOI：10.1109/JSSC.2017.2744618

• Auto zero
• current sharing
• dc-dc converter
• digital frequency synchronization (DFS)
• duty-cycle-calibrated delay line (DCC-DL)
• hysteretic control
• multi-phase buck converter
• online offset calibration
• phase synchronization
• quasi-current mode
• switching power supply

A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than +/- 1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables +/- 1.1% voltage regulation accuracy. Maximum current-sharing error of +/- 3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc-dc converter achieves 93% peak efficiency for V-i = 2 V and V-o = 1.6 V.

• 出版日期2017-11