A Low-Latency, High-Throughput On-Chip Optical Router Architecture for Future Chip Multiprocessors

作者：Cianchetti Mark J^*; Albonesi David H

来源：ACM Journal on Emerging Technologies in Computing Systems, 2011, 7(2): 9.

DOI：10.1145/1970406.1970411

• Interconnect architecture
• multiprocessor network
• optical interconnect
• optical switch

Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible na.nophotonics has emerged as a leading candidate for replacing global wires beyond the 16nm timeframe, on-chip optical interconnect architectures are typically limited in scalability or are dependent on comparatively slow electrical control networks.
In this article, we present a hybrid electrical/optical router for future large scale, cache coherent multicore microprocessors. The heart of the router is a low-latency optical crossbar that uses predecoded source routing and switch state preconfiguration to transmit cache-line-sized packets several hops in a single clock cycle under contentionless conditions. Overall, our optical router achieves 2X better network performance than a state-of-the-art electrical baseline in a mesh topology while consuming 30% less network power.

• 出版日期2011-6