A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

作者：Kim Shinwoong^*; Hong Seunghwan; Chang Kapseok; Ju Hyungsik; Shin Jaewook; Kim Byungsub; Park Hong June; Sim Jae Yoon^*

来源：IEEE Journal of Solid-State Circuits, 2016, 51(2): 391-400.

DOI：10.1109/JSSC.2015.2494365

• All-digital
• frequency synthesizer
• fractional-N
• phase-locked loop
• standard cell
• synthesis
• time-to-digital converter (TDC)

This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of 0.047 mm(2) and achieves a stable in-band phase noise of lower than -100 dBc/Hz in a wide range of supply voltage from 1 to 1.4 V.

• 出版日期2016-2