Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

作者：Sakimura Noboru^*; Sugibayashi Tadahiko; Nebashi Ryusuke; Kasai Naoki

来源：IEEE Journal of Solid-State Circuits, 2009, 44(8): 2244-2250.

DOI：10.1109/JSSC.2009.2023192

• MRAM
• nonvolatile flip-flops
• standby-power reduction

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150 nm, 1.5 V CMOS and 240 nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.

• 出版日期2009-8