A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS

作者：Cai Shengchang^*; Tabasy Ehsan Zhian; Shafik Ayman; Kiran Shiva; Hoyos Sebastian; Palermo Samuel

来源：IEEE Journal of Solid-State Circuits, 2017, 52(8): 2168-2179.

DOI：10.1109/JSSC.2017.2689033

• Analog-to-digital converter (ADC)
• comparators
• metastability
• multi-bit search
• soft-decision selection
• time interleaving

While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable flexible and powerful digital signal processing-based (DSP-based) equalization, the robustness and power consumption of these ADCs can limit overall receiver energy efficiency. This paper presents a 25 GS/s 6b 8-way time-interleaved multi-bit search ADC that employs a soft-decision selection algorithm to relax track-and-hold (T/H) settling requirements and improve ADC metastability tolerance. T/H bandwidth is also improved with a new shared-input double-tail three-latch structure. Fabricated in general purpose 65 nm CMOS, the ADC occupies 0.24 mm(2) total area. A signal-to-noise and distortion ratio (SNDR) of 29.6 dB is achieved at Nyquist while consuming 88 mW from a 1 V supply, translating into a figure-of-merit of 143 fJ/conversion step. A measured <10(-10) metastability error rate demonstrates the effectiveness of the soft-decision selection algorithm.

• 出版日期2017-8