Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis

作者：Gholipour Morteza^*; Chen Ying Yu^*; Sangai Amit^*; Masoumi Nasser^*; Chen Deming^*

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(2): 650-663.

DOI：10.1109/TVLSI.2015.2406734

• Graphene nanoribbon field-effect transistor (GNRFET)
• nanoelectronics
• Schottky barrier (SB)
• SPICE model

This paper presents an accurate analytical compact model for Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. The proposed model considers various design parameters and process variation effects, including graphene-specific line-edge roughness, which allows thorough exploration and evaluation of SB-GNRFET circuits. We develop accurate approximations of SB tunneling, channel charge, and current, which provide accurate results while maintaining model compactness. We evaluate the effect of design parameters and process variations on the performance of SB-GNRFETs. We also compare circuit-level performance of SB-GNRFETs with multigate (MG) Si-CMOS (e.g., FinFETs). Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS, although GNR-specific process variation, especially the line-edge roughness, would significantly downgrade such an advantage; the EDP of the ideal SB-GNRFET (assuming no process variation) is similar to 2.5% of that of Si-CMOS, while the EDP of the nonideal case with process variation is similar to 68% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (nonideal) SB-GNRFET is similar to 0.88% (54%) EDP of that of Si-CMOS as the technology nodes scale down to 7 nm.

• 出版日期2016-2