Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

作者：Yan, Aibin^*; Lai, Chaoping; Zhang, Yinlei; Cui, Jie; Huang, Zhengfeng; Song, Jie; Guo, Jing; Wen, Xiaoqing

来源：IEEE Transactions on Emerging Topics in Computing, 2021, 9(1): 520-533.

DOI：10.1109/TETC.2018.2871861

• Latches
• Inverters
• Clocks
• Feedback loop
• MOSFET
• Robustness
• Circuit reliability
• radiation hardening
• triple-node upset
• double-node upset
• single node upset
• soft error

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

• 出版日期2021-1-1
• 单位中北大学; 安徽大学; 合肥工业大学