System-Level ESD Protection Design Using On-Wafer Characterization and Transient Simulations

作者：Scholz Mirko^*; Chen Shih Hung; Thijs Steven; Linten Dimitri; Hellings Geert; Vandersteen Gerd; Sawada Masanori; Groeseneken Guido

来源：IEEE Transactions on Device and Materials Reliability, 2014, 14(1): 104-111.

DOI：10.1109/TDMR.2012.2201720

• Electrostatic discharge (ESD)
• integrated circuit (IC) reliability
• reliability
• system analysis and design

A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solution can be verified long before IC packaging and even before the final system is built.

• 出版日期2014-3