科研之友
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摘要
The design of heterostructures that exhibit desired strain characteristics is critical for the realization of semiconductor devices with improved performance and reliability. The control of strain and dislocation dynamics requires an understanding of the relaxation processes associated with mismatched epitaxy, and the starting point for this analysis is the equilibrium strain profile, because the difference between the actual strain and the equilibrium value determines the driving force for dislocation glide and relaxation. Previously, we developed an electrical circuit model approach for the equilibrium analysis of semiconductor heterostructures, in which an epitaxial layer may be represented by a stack of subcircuits, each of which involves an independent current source, a resistor, an independent voltage source, and an ideal diode. In this work, we have applied the electrical circuit model to study the strain compensation mechanism and show that, for a given compositionally uniform device layer with fixed mismatch and layer thickness, a buffer layer may be designed (in terms of thickness and mismatch) to tailor the strain in the device layer. A special case is that in which the device layer will exhibit zero residual strain in equilibrium (complete strain compensation). In addition, the application of the electrical circuit analogy enables the determination of exact expressions for the residual strain characteristics of both the buffer and device layers in the general case where the device layer may exhibit partial strain compensation. On the basis of this framework, it is possible to develop design equations for the tailoring of the strain in a device layer grown on a uniform composition buffer.
- 出版日期2017-12
