A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology

作者：Yi Xiang^*; Boon Chirn Chye; Liu Hang; Lin Jia Fu; Lim Wei Meng

来源：IEEE Journal of Solid-State Circuits, 2014, 49(2): 347-359.

DOI：10.1109/JSSC.2013.2293021

• CMOS
• frequency synthesizer
• in-phase injection-coupled (IPIC)
• low phase error
• low phase noise
• low power
• millimeter-wave
• PLL
• quadrature voltage-controlled oscillator (QVCO)
• 60 GHz

A fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) is proposed. Through a particular symmetrical coupling network formed by diode-connected transistors, the in-phase coupling is realized in the IPIC-QVCO, which reduces both phase noise and phase error. A compact inductor-less divider chain is designed to reduce power consumption. A self-correcting low spur charge pump is employed to reduce reference spur. A standalone 60 GHz IPIC-QVCO and a fully integrated PLL are implemented in standard 65 nm low power CMOS technology. The measurement results show that the QVCO covers a frequency range from 57.88 to 68.33 GHz while consuming 11.4 mW power from a 1.2 V supply. The phase noise of the QVCO is -92 similar to -95 dBc/Hz at 1 MHz offset. The FOM and FOMT of the QVCO are -178.1 similar to -179.7 and -182.5 similar to -184.1 dBc/Hz respectively. The tuning range of the frequency synthesizer is from 57.9 to 68.3 GHz, and the power consumption is 24.6 mW. The phase noise of the frequency synthesizer is -89.8 similar to -91.5 dBc/Hz at 1 MHz offset across the frequency band.

• 出版日期2014-2
• 单位南阳理工学院