Deposited Thin SiO(2) for Gate Oxide on n-Type and p-Type GaN

作者：Placidi M^*; Constant A; Fontsere A; Pausas E; Cortes I; Cordier Y; Mestres N; Perez R; Zabala M; Millan J; Godignon P; Perez Tomas A

来源：Journal of the Electrochemical Society, 2010, 157(11): H1008-H1013.

DOI：10.1149/1.3486091

Here, we report on a comparison of two different methods to achieve thin SiO(2) deposited layers for gate oxide on n- and p-type GaN by using plasma-enhanced chemical vapor deposition with silane (SiH(4)) and tetraethyl orthosilicate (Si[OC(2)H(5)](4)) precursors. An annealing was performed at 800 degrees C for 2 min in N(2) ambient as an attempt to improve electrical characteristics. Before and after annealing, capacitors were electrical/physically analyzed by capacitance-voltage (C-V), conductance-voltage, current-voltage, optical microscope, scanning electron microscope, atomic force microscope, and secondary-ion mass spectrometry. Globally, the p-type samples presented higher interface state density and rougher surfaces, and in some C-V measurements, it is possible to observe inversion-like characteristics. The surface roughness also increases after annealing. The interfacial trap density for the different SiO(2)/GaN interfaces has been determined. Silane samples exhibit lower D(it) than TEOS samples. For n-type, annealed SiO(2) from silane has been found as the sample with the lowest D(it). The annealing on the SiO(2) from silane samples is not so efficient for the p-type with the D(it) actually increasing. A discussion on the different diffusion mechanisms in correlation with the electrical results is performed in the last section of this paper.

• 出版日期2010