A low-power high-speed true single phase clock divide-by-2/3 prescaler

作者：Wu Jianhui^*; Wang Zixuan; Ji Xincun; Huang Cheng

来源：IEICE Electronics Express, 2013, 10(2): 20120913.

DOI：10.1587/elex.10.20120913

• prescaler
• TSPC
• high-speed
• low-power
• CMOS

A novel low power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18 mu m CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10 GHz with 1.836 mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8 GHz with 1.34 mW power consumption.

• 出版日期2013
• 单位南京大学; 东南大学