A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme

作者：Lee Won Young^*; Hwang Kyu Dong; Kim Lee Sup

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59(12): 2858-2866.

DOI：10.1109/TCSI.2012.2206456

• Clock and data recovery
• equalizer
• multi-rate operation

A 5.4/2.7/1.62-Gb/s multi-rate receiver is designed for DisplayPort version 1.2. A dual-mode binary phase detector supports half-rate and quarter-rate phase detections to enable the multi-rate operation of the receiver without a wide-tuning VCO. In addition, a low voltage-drop active inductor with a voltage booster is implemented in the dual-mode binary phase detector to extend the bandwidth and reduce the power consumption. The voltage booster generates 1.904 V from 1.2-V supply with fast voltage generation time and small area consumption. A bandwidth controllable equalizer is proposed to optimize channel loss compensation even if the Nyquist frequency of input data changes. The BER for all input data rates is less than 10(-12) for 2(7)-1 PRBS and the measured jitter characteristics indicate that the proposed receiver exceeds the DisplayPort jitter tolerance specification. The recovered 1.35-GHz clock shows the peak-to-peak jitter of 29.9 ps and the rms jitter of 3.215 ps for 5.4-Gb/s input. The energy efficiency of the CDR circuit in the receiver is 19.3 pJ/bit at 5.4 Gb/s. The receiver occupies 0.672 mm(2) including decoupling capacitors and the CDR core area is 0.44 mm(2)

• 出版日期2012-12