A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS

作者：Furuta Masanori^*; Akita Ippei; Matsuno Junya; Itakura Tetsuro

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2013, E96A(7): 1552-1561.

DOI：10.1587/transfun.E96.A.1552

• time-interleaved
• SAR
• ADC
• dynamic
• T/H circuit
• high-speed
• low-power

This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14 mm(2) and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.

• 出版日期2013-7