A parallel camera image signal processor for SIMD architecture

作者：Choi Seung Hyun; Cho Junguk; Tai Yong Min; Lee Seong Won^*

来源：EURASIP Journal on Image and Video Processing, 2016, 2016(1): 29.

DOI：10.1186/s13640-016-0137-2

• CMOS image sensor
• Image signal processor
• Reconfigurable processor
• Parallel processing optimization

An image signal processor (ISP) for a camera image sensor consists of many complicated functions; in this paper, a full chain of the ISP functions for smart devices is presented. Each function in the proposed ISP full chain is designed to handle high-quality images. Every function in the chain is fully converted to a fixed-point arithmetic, and a special function is not used for easy porting to a Samsung Reconfigurable Processor (SRP). Several parallelizing optimization techniques are applied to the proposed ISP full chain for real-time operation on a given 600-MHz reconfigurable processor. To verify the performance of the proposed ISP full chain, a series of tests was performed, and all of the measured values satisfy the quality and performance requirements.

• 出版日期2016-9-30