Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS

作者：Liu Jian^*; Wang Xin; Zhao Hui; Fang Qiang; Wang Albert; Lin Lin; Tang He; Fan Siqiang; Zhao Bin; Wen Shi Jie; Wong Richard

来源：IEEE Journal of Solid-State Circuits, 2011, 46(5): 1100-1110.

DOI：10.1109/JSSC.2011.2118290

• ESD protection
• dual-direction
• SCR
• VLTdSCR
• CULTdSCR
• ESD-critical parameters
• cross-coupling
• RF
• CMOS

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 mu m CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (V(t1)) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (C(ESD)) of 150 fF and prompt response to very fast ESD pulses with rising time (t(r)) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of similar to 7 V/mu m(2).

• 出版日期2011-5