An SDRAM-Aware Router for Networks-on-Chip

作者：Jang Wooyoung^*; Pan David Z

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(10): 1572-1585.

DOI：10.1109/TCAD.2010.2061251

• Flow control
• memory
• networks-on-chip
• router
• scheduler

Networks-on-chip (NoCs) may interface with lots of synchronous dynamic random access memories (SDRAM) to provide enough memory bandwidth and guaranteed quality-of-service for future systems-on-chip (SoCs). SDRAM is commonly controlled by a memory subsystem that schedules memory requests to improve memory efficiency and latency. However, a memory subsystem is still a performance bottleneck in the entire NoC. Therefore, memory-aware NoC optimization has attracted considerable attention. This paper presents a NoC router with an explicit SDRAM-aware flow control. Based on priority-based arbitration, our SDRAM-aware flow controller schedules memory requests to prevent bank conflict, data contention, and short turn-around bank interleaving. Moreover, our multi-stage scheduling scheme further improves memory performance and saves NoC hardware costs. Experimental results show that our cost-efficient SDRAM-aware NoC design significantly improves memory latency and utilization compared to the conventional NoC design with no SDRAM-aware router.

• 出版日期2010-10