Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of Power Electronics Designs

作者：Majstorovic Dusan^*; Celanovic Ivan; Teslic Nikola Dj; Celanovic Nikola; Katic Vladimir A

来源：IEEE Transactions on Industrial Electronics, 2011, 58(10): 4708-4716.

DOI：10.1109/TIE.2011.2112318

• Automatic design verification
• electronic design automation for power electronics (PE)
• field-programmable gate array (FPGA)-based ultralow-latency (ULL) processor
• hardware in the loop (HIL)
• real-time digital simulator for PE and motor drives

This paper introduces a unified approach to the validation of power-electronics (PE) control hardware, firmware, and software designs. It is based on a scalable application-specific ultralow-latency (ULL) digital processor core. The proposed ULL processor core simulates PE converters and systems comprising multiple power converters with a fixed 1-mu s simulation time step and latency, regardless of the size of the system. Owing to its ULL, the proposed platform enables the fully automatic testing and validation of the complete PE design comprising component safe-operating-area validation, system protection, firmware, and software implementation as well as overall system performance optimization.

• 出版日期2011-10