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摘要
In this paper, a flexible CABAC encoder architecture for H.264/AVC encoder applications up to UHDTV (7680x4320) resolution is proposed. Stages of CABAC encoding are analyzed and a generalized CABAC architecture is designed. The parallel binarizer and context modeler (BCM) and multi-symbol binary arithmetic coder (MSBAC) is coupled together by a variable throughput buffer and packers (VTBAP) for throughput matching. Syntax elements (SEs) are analyzed thoroughly and various SEs processing engines are proposed to achieve parallelism for performance with high degree of flexibility for CABAC designers. Special attentions have been paid to the feeding of SEs into BCM that is not discussed in most other works. Without the bubble-free access control and the bubble-free feeding of SEs, the high throughput of BCM and MSBAC engine will not be possible to integrate with the rest of the encoder engine, otherwise external pre-processing has to be applied for SEs feeding. Flexibilities of architecture and level of parallelism are incorporated into a CABAC auto generating scheme that can produce the CABAC configurations according to user requirements. Towards a 0.13 mu m CMOS technology, the highest performance design generated by the automatic generation scheme can encode 4.86 bins per cycle on the average, and it provides a throughput of 1234 Mbin/s. The proposed CABAC encoder architecture has been integrated into a H.264/AVC encoder of a multimedia SoC successfully(1).
- 出版日期2012-11
- 单位中国科学院电工研究所
