A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators-Analysis, Design, and Measurement Techniques

作者：Elshazly Amr^*; Rao Sachin; Young Brian; Hanumolu Pavan Kumar

来源：IEEE Journal of Solid-State Circuits, 2014, 49(5): 1184-1197.

DOI：10.1109/JSSC.2014.2305651

• Calibration-free
• CMOS digital integrated circuits
• digital phase-locked loops (DPLLs)
• low power
• noise-shaping time-to-digital converter (TDC)
• oversampling
• SRO-TDC
• switched-ring oscillator (SRO)
• TDC measurement techniques
• two-frequency-switching TDC

A high-resolution time-to-digital converter (TDC) using switched-ring oscillators (SROs) is presented. Leveraging oversampling and noise shaping, the proposed SRO-TDC achieves high resolution without the need for calibration. Ring oscillators are switched between two frequencies to achieve noise shaping of the quantization error in an open-loop manner. By decoupling the sampling clock and input carrier frequencies, SRO-TDC is capable of operating at high oversampling ratios (OSRs). This paper also discusses different noise sources and quantization/device noise tradeoffs in noise-shaping TDCs and presents techniques to characterize TDC linearity, range, and noise performance. Fabricated in 90 nm CMOS technology, the proposed TDC operates over a wide range of input carrier frequencies (0.6-750 MHz) and sampling rates (50-750 MS/s). At 500 MS/s and 80 MHz carrier frequency, it achieves an integrated noise of 315 fs in a 1 MHz bandwidth while consuming 1.5 mW from a 1 V supply. The SRO-TDC occupies an active die area of only 0.02 mm(2).

• 出版日期2014-5