A 0.5-V 5.9-fJ/Conversion-Step SAR ADC in 0.18-mu m CMOS

作者：Ren, Xiaojiao^*; Zhuang, Yiqi; Li, Xiaoming; Qi, Zengwei; Wang, Bo

来源：IEEJ Transactions on Electrical and Electronic Engineering, 2016, 11(4): 467-473.

DOI：10.1002/tee.22263

• successive approximation register analog-to-digital converter (SAR ADC)
• ultralow power
• switching sequence
• fully dynamic comparator
• bootstrapped switch
• CMOS

In this paper, we present a 434-nW 8-bit successive approximation register analog-to-digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split-capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 CVref2 for the single-ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 mu m EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal-to-noise-plus-distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step.

• 出版日期2016-7
• 单位西安电子科技大学