A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

作者：Sze Vivienne^*; Finchelstein Daniel F; Sinangil Mahmut E; Chandrakasan Anantha P

来源：IEEE Journal of Solid-State Circuits, 2009, 44(11): 2943-2956.

DOI：10.1109/JSSC.2009.2028933

• Video codecs
• H.264/AVC
• CMOS digital integrated circuits
• low-power electronics
• cache memories
• SRAM chips
• CMOS memory circuits

The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7 V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 mu W.

• 出版日期2009-11