Automatic Pipelining From Transactional Datapath Specifications

作者：Nurvitadhi Eriko^*; Hoe James C; Kam Timothy; Lu Shih Lien L

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(3): 441-454.

DOI：10.1109/TCAD.2010.2088950

• Automatic pipelining
• datapath specification
• design space exploration
• hardware synthesis
• x86 pipelines

This paper presents a transactional specification framework (T-spec) for describing a datapath and the tool T-piper to synthesize automatically an in-order pipelined implementation with arbitrary user-specified pipeline-stage boundaries. T-spec abstractly views a datapath as executing one transaction at a time, computing the next system states based on the current ones. The synthesized pipeline maintains this semantics, yet allows concurrent execution of multiple overlapped transactions in different pipeline stages, where each stage performs a part of the next-state computation of each transaction. T-spec makes the state reading and writing events in a datapath explicit to enable T-piper to perform exact read-after-write (RAW) hazard analysis between the overlapped transactions. T-piper can automatically generate the pipeline control not only to ensure the correctness of the pipelined executions but also to minimize (using forwarding and speculation) the performance loss due to pipeline stalls in the presence of RAW dependencies. This paper reports design case studies applying T-spec and T-piper to reduced instruction set computing and complex instruction set computing processor pipeline development. In the latter, we report the results from a rapid design space exploration of 60 generated x86-subset pipelines, varying in pipeline depth, forwarding, and speculative execution, all starting from a single T-spec.

• 出版日期2011-3