摘要

This paper presents a four-phase buck converter with capacitor-current-sensor (CCS) calibration for load-transient-response optimization that targets the theoretically minimal output-voltage undershoot Delta V-US, overshoot Delta V-OS, and settling time t(S) when large and rapid load-current transients Delta I-load occur. The proposed CCS calibration calibrates the CCS' equivalent impedance to emulate a scaled replica of the output capacitor's impedance Z(Co). Thus, the CCS can accurately sense the output-capacitor current I-Co despite Z(Co) variations due to different output voltages, fabrication variations, and printed-circuit-board parasitics. Moreover, a load-transient optimizer is proposed to utilize the accurately sensed I-Co to instantly detect the large and rapid Delta I-load, and synchronously control the charging and discharging durations of the output inductors in all four phases, resulting in small Delta V-US/Delta V-OS and short t(S). The converter is implemented in a 0.18-mu m CMOS process with 1.93-mm(2) chip area. For a 1.8-A/5-ns step-up (step-down) Delta I-load, the measured Delta V-US (Delta V-OS) and t(S) are 92 mV (75 mV) and 133 ns (110 ns), respectively. Compared with other state-of-the-arts, both the measured Delta V-US (Delta V-OS) and tS in this paper are the closest to their respective theoretical limits, i.e., the fastest load-transient response with the smallest Delta V-US (Delta V-OS) and the shortest t(S) under the same input voltage, output voltage, output inductance, and output capacitance.

  • 出版日期2018-2