A 6-bit Segmented DAC Architecture With up to 56-GHz Sampling Clock and 6-V-pp Differential Swing

作者：Balteanu Andreea^*; Schvan Peter; Voinigescu Sorin P

来源：IEEE Transactions on Microwave Theory and Techniques, 2016, 64(3): 881-891.

DOI：10.1109/TMTT.2016.2525825

• Current steering
• digital-to-analog converter (DAC)
• distributed amplifiers (DAs)
• power DAC
• segmented DAC
• SiGe BiCMOS

A distributed power digital-to-analog converter (DAC) architecture with multi-level segmentation is proposed. Due to its large output voltage swing, it can be used as a large swing arbitrary waveform generator suitable for a variety of wireline, fiber optic, and instrumentation applications. A proof-of-concept 56-GS/s 6-bit implementation with most significant bits (MSBs) and least significant bits (LSBs) segmentation and full-rate clock was manufactured in a production 130-nm SiGe BiCMOS technology. The circuit features 14 independent data bits-seven for the three MSBs and seven for the three LSBs-each running at up to at least 44 Gb/s. The measured saturated output power and bandwidth are 17 dBm and 45 GHz, respectively. An output swing of 3.4 V-pp per side is observed in 50-Omega loads. Spectral measurements demonstrate multi-bit modulation at carrier frequencies as high as 56 GHz. To the best of our knowledge, this marks the highest output-bandwidth highest voltage-swing current-steering DAC in silicon.

• 出版日期2016-3