A new approach to single event effect tolerance based on asynchronous circuit technique

作者：Gong, Rui^*; Chen, Wei; Liu, Fang; Dai, Kui; Wang, Zhiying

来源：Journal of Electronic Testing-Theory and Applications, 2008, 24(1-3): 57-65.

DOI：10.1007/s10836-007-5029-z

• SEE tolerance
• asynchronous circuit
• SEU tolerance
• SET tolerance

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 mu m process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.

• 出版日期2008-6
• 单位中国人民解放军国防科学技术大学