An NTF-enhanced incremental Sigma Delta modulator using a SAR quantizer

作者：Hojati Zeinab; Yavari Mohammad^*

来源：Integration, the VLSI Journal, 2016, 55: 212-219.

DOI：10.1016/j.vlsi.2016.06.006

• Incremental data converters
• Sigma-delta modulators
• Charge redistribution SAR ADCs
• Error-feedback
• Noise-shaping
• Switched-capacitor circuits

In this paper, a noise transfer NTF) enhanced incremental sigma-delta (Sigma Delta) modulator is presented. It employs a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) in an error-feedback scheme to achieve an extra noise-shaping order. Using a multi-bit SAR quantizer not only improves the stability and power consumption but also facilitates the realization of both the adder situated in front of the quantizer and the whole error-feedback loop. As a design example, a multiplexed 2nd-order modulator based on the proposed architecture is simulated in TSMC 90 nm CMOS technology using Spectre with a 1 V single power supply. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 85.3 dB within a signal bandwidth of 20 kHz (1 kHz/channel) at 5 MHz sampling frequency. The power consumption for each channel is 8.6 mu W.

• 出版日期2016-9