Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

作者：Jeon Dongsuk^*; Seok Mingoo; Zhang Zhengya; Blaauw David; Sylvester Dennis

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2012, 59(12): 952-956.

DOI：10.1109/TCSII.2012.2231036

• Error-tolerant system
• K-best decoder
• low-power circuit design
• voltage overscaling

This paper proposes a design methodology for voltage overscaling (VOS) of ultra-low-power systems. This paper first proposes a probabilistic model of the timing error rate for basic arithmetic units and validates it using both simulations and silicon measurements of multipliers in 65-nm CMOS. The model is then applied to a modified K-best decoder that employs error tolerance to reveal the potential of the framework. With simple modifications and timing error detection-only circuitry, the conventional K-best decoder improves its error tolerance in child node expansion modules by up to 30% with less than 0.4-dB SNR degradation. With this error tolerance, the supply voltage can be overscaled by 12.1%, leading to 22.5% energy savings.

• 出版日期2012-12