SOI high-voltage LDMOS with novel triple-layer top silicon based on thin BOX

作者：Hu S D^*; Zhang L; Luo J; Tan K Z; Chen W S; Gan P; Zhou X C; Zhu Z

来源：Electronics Letters, 2013, 49(3): 223-224.

DOI：10.1049/el.2012.2988

A novel SOI high-voltage LDMOS with a triple-layer top silicon (TLTS) is investigated. The top silicon layer of the TLTS LDMOS consists of n(-) silicon with a p-top layer, p(-) silicon in the middle, and n(+) silicon on the interface. On the condition of high-voltage blocking state, the electric fields of the drift region and BOX are modulated and optimised by the triple-layer top silicon, respectively, which induces a high BV of 624 V for the TLTS LDMOS with a thin buried oxide layer (BOX) of 0.4 mu m. Compared with several SOI devices, the proposed TLTS LDMOS has a higher figure-of-merit.

• 出版日期2013-1-31
• 单位重庆大学