A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass Sigma Delta ADC in 0.13 mu m CMOS

作者：Gupta Subhanshu^*; Gangopadhyay Daibashish; Lakdawala Hasnain; Rudell Jacques C; Allstot David J

来源：IEEE Journal of Solid-State Circuits, 2012, 47(5): 1141-1153.

DOI：10.1109/JSSC.2012.2185530

• Charge pump
• direct-RF sigma-delta ADC
• direct sampling RF
• finite-impulse response DAC
• harmonic-rejection injection-locked oscillator
• integer-N phase-locked loop
• narrowband programmable LNA
• reconfigurable
• reference spur
• SDR

A reconfigurable bandpass continuous-time Sigma Delta RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 mu m CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is -74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz.

• 出版日期2012-5