A Self-Testing Platform with a Foreground Digital Calibration Technique for SAR ADCs

作者：Juan, Yi-Hsiang; Huang, Hong-Yi; Lee, Shuenn-Yuh; Lai, Shin-Chi; Juang, Wen-Ho; Luo, Ching-Hsing^*

来源：Applied Sciences-Basel, 2016, 6(8): 217.

DOI：10.3390/app6080217

• analog-to-digital converters (ADCs)
• digital calibration method
• self-testing
• successive approximation register ADC (SAR)

This study presents a self-testing platform with a foreground digital calibration technique for successive approximation register (SAR) analog-to-digital converters (ADCs). A high-accuracy digital-to-analog converter (DAC) with digital control is used for the proposed self-testing platform to generate the sinusoidal test signal. This signal is then implemented using an Arduino board, and the clock signal is generated to test the ADCs. In addition, fast Fourier transform and recursive discrete Fourier transform (RDFT) processors are adopted for dynamic performance evaluation and calibration of the ADCs. The third harmonic distortion caused by the non-linearity of the track-and-hold circuit, the mismatch of the DAC capacitor array, and the direct current (DC) offset of the comparator can be calculated using the processors to improve the ADC performance. The advantages of the proposed platform include its low cost, high integration, and no need for an extra analogy compensation circuit to deal with calibration. In this work a 12 bit SAR ADC and an RDFT processor are used in the Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) 0.18 mu m standard complementary metal-oxide-semiconductor (CMOS) process with a sampling rate of 18.75 kS/s to validate the proposed method. The measurement results show that the signal-to-noise and distortion ratio is 55.07 dB before calibration and 61.35 dB after calibration.

• 出版日期2016-8
• 单位南华大学