A 1.92-Megapixel CMOS Image Sensor With Column-Parallel Low-Power and Area-Efficient SA-ADCs

作者：Shin Min Seok^*; Kim Jong Boo; Kim Min Kyu; Jo Yun Rae; Kwon Oh Kyong

来源：IEEE Transactions on Electron Devices, 2012, 59(6): 1693-1700.

DOI：10.1109/TED.2012.2190936

• CMOS image sensor
• column-parallel readout architecture
• low-power consumption
• small-area successive approximation analog-to-digital converter (SA-ADC)

This paper presents a CMOS image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is 9 mu\m x 425 mu m. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-mu m CMOS process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively.

• 出版日期2012-6