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摘要
An analogue equaliser with a novel digitally tuned variable degeneration resistance is realised in a 65 nm CMOS technology. Implemented with three parallel resistance branches and one serial resistance branch to well fit the optimal conductance curve, the proposed variable degeneration resistance is exploited to achieve a wide boost range while significantly improving the linearity of the tuned boost factors compared with the equaliser with a traditional degeneration resistance structure.
- 出版日期2015-5-14
- 单位北京大学
