A Novel V-DSAT Extraction Method for Tunnel FETs and Its Implication on Analog Design

作者：Acharya Abhishek^*; Dasgupta Sudeb; Anand Bulusu

来源：IEEE Transactions on Electron Devices, 2017, 64(2): 629-633.

DOI：10.1109/TED.2016.2635688

• Amplifier design
• analog performance
• drain current saturation
• nanowire TFET
• V-DSAT extraction technique

This brief investigates for the first time, a method to extract the value of saturation drain voltage for a tunnel FET. The saturation in output characteristics of a TFET is found to take place when the difference in conduc-tion band energy (Delta E-C) of channel (E-CC) and drain (E-CD) is a few KBT. As the drain voltage (V-DS) increases, it is found that the device initially enters in a soft saturation state and sub-sequently into deep saturation. For any given value of gate voltage (V-GS), the onset of soft and deep saturationhappens for a constant difference in V-GS and V-DS. We propose a novel method to extract this voltage difference V-GD, which is explained using a phenomenological approach. We have also validated our results with published experimental data. It is found that the output resistance (R-o), transconduc-tance (g(m)), and intrinsic gain (g(m) x R-o) increase when the device enters in a soft saturation and attain a maximum value in deep saturation regime. Furthermore, a common source amplifier biased in soft saturation is also demon-strated to have a comparable voltage gain and bandwidth to the one biased in deep saturation.

• 出版日期2017-2