An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC

作者：Zhu, Yan^*; Chan, Chi-Hang; U, Seng-Pan; Martins, R. P.

来源：40th European Solid-State Circuit Conference (ESSCIRC), 2014-09-22 To 2014-09-26.

DOI：10.1109/ESSCIRC.2014.6942059

• GS/S

This paper presents a sub-ranging 6-way time-interleaved pipelined-SAR ADC that achieves 900MS/s and 9.3 ENOB in 65nm CMOS. The architecture optimization is based on a pipelined-SAR structure that obtains high-speed with an optimized number of channels, thus leading to relaxed calibration with higher efficiency in power and area consumption. The proposed channel-selection-embedded bootstrap performs sampling instants synchronization without additional components, thus effectively suppressing the spurs from time skews below -65 dBFS. The mismatch errors due to offset and gain are all solved on-chip, whose spurs are suppressed below -67 dBFS. The prototype achieves 66 dB SFDR and 51.5 dB SNDR with a Nyquist input exhibiting a FoM of 56 fJ/conv.step.

• 出版日期2014
• 单位澳门大学