A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10-and 40-GbE Links

作者：Yoon Taehun^*; Lee Joon Yeong; Lee Jinhee; Han Kwangseok; Lee Jeong Sup; Lee Sangeun; Kim Taeho; Han Jinho; Won Hyosup; Park Jinho; Bae Hyeon Min

来源：IEEE Journal of Solid-State Circuits, 2017, 52(3): 688-703.

DOI：10.1109/JSSC.2016.2636858

• 10 GbE
• 40 GbE
• 100 GbE
• CDR
• delay- and phase-locked loop (D/PLL)
• low power
• MLG 2.0
• multilink gearbox (MLG)
• reference less
• reverse gearbox IC
• transceiver

This paper presents the first 103.125-Gb/s multilink gearbox (MLG) IC, which facilitates the transport of independent 10-and 40-GbE signals to 4 x 25.78 Gb/s physical layers, such as 100GBASE-xR4. The IC consumes only 1.37 W while implementing complicated reverse gearbox functionality. The measured TX jitter from 10- and 25-G lanes is 0.407 and 0.448 psrms, respectively. The measured input sensitivities for a BER of 10(-1)2 of the 10- and 25-G RXs are 20 and 42 mVppd, respectively. The proposed gearbox IC, fabricated in a 40-nm CMOS process, occupies 3.7x3.4 mm(2). The power consumption of RX and TX in a 25-G interface is 50.9 and 52 mW, respectively, and those of a 10-G interface are 29 and 24.4 mW, respectively. MLG functionality is verified using embedded self-test logics.

• 出版日期2017-3