A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

作者：Rahman Wahid^*; Yoo Danny; Liang Joshua; Sheikholeslami Ali; Tamura Hirotaka; Shibasaki Takayuki; Yamaguchi Hisakatsu

来源：IEEE Journal of Solid-State Circuits, 2017, 52(12): 3517-3531.

DOI：10.1109/JSSC.2017.2744661

• Baud rate
• clock and data recovery (CDR)
• continuous-time linear equalizer (CTLE)
• decision feedback equalizer (DFE)
• digital CDR
• frequency detection
• referenceless CDR

This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency detection and frequency correction. Frequency detection is achieved by examining rising and falling data waveforms to detect discrepancies between the data rate and the locally recovered clock frequency. Frequency correction uses digitally adjustable asymmetry of the proposed adjustable baud-rate phase detector to correct any frequency error. The receiver is implemented in the TSMC 28-nm CMOS process with an analog front end consisting of a CTLE, sampling comparators, a digitally controlled oscillator, and a digital back end consisting of synthesized digital CDR logic. The open-loop frequency detector range is measured to be 39%. The closed-loop CDR capture range is measured to be 34%, limited by test equipment. The proposed frequency acquisition scheme improves the measured CDR capture range by up to 227x. At 32 Gb/s, the entire receiver consumes 102.04 mW, achieving energy consumption below 3.19 pJ/b.

• 出版日期2017-12